1. Field of the Invention
The present invention relates generally to integrated circuit technology, more specifically to integrated circuit fabrication processes and, in particular, to an etch process and product which have improved critical dimension control.
2. Description of Related Art
In order to fabricate the complex, three-dimensional structure of an integrated circuit, the execution of a relatively large number of individual and complex interactive operations is required. It is well known to use photolithographic techniques in order to achieve the very small dimensions of the individual components, namely, the millions of transistors, interconnects, and the like, that make up one integrated circuit (commonly and hereinafter also referred to as a "die" or a "chip)" which itself is perhaps only 5-millimeters per side. Fundamentally, photolithography is used in performing masking processes that allow etching and ionic implanting manipulations of selected regions of a semiconductor substrate. The photolithographic process for a single wafer of chips requires repeated transfers of images via the use of a set of photosensitive masks (known as and hereinafter also referred to as "photoresist" or simply "resist") to a semiconductor wafer.
There is an ever constant demand for more powerful integrated circuits, meaning more circuit components within the same size or smaller chip. Very large scale integration ("VLSI") in integrated circuit technology has resulted in chips in which the geometry of individual components is continuously scaled downward in order to provide more complex integrated circuits, to improve performance, and to conserve chip area for better manufacturing yield, using substantially the same die sizes. Integrated circuit fabrication process specific design rules are commonly referred to in terms relating to aspects of the dimensions of certain regions of a particular circuit. A popular measure is "channel length" or "gate length" of a field effect transistor, e.g., a "0.5-micron process." A specific set of design rules for a specific generation of VLSI is also referred to hereinafter more simply as a "process generation."
A problem with current photolithographic techniques is that there appears to be a limit to the size component feature that can be achieved. For example, using deep ultraviolet photolithography, the smallest feature that theoretically can be fabricated in the state-of-the-art is about 0.2-micron, or 200-nanometers ("nm"). Primary problems in achieving greater resolution with current optical imaging equipment appear to be due to the formation of standing wave patterns generated in the photoresist, the change in focus of projected images, and light scattering and lateral exposure that causes changes in the width of individual regions of the structure. All of these factors can result in individual component alignment errors.
In order to achieve a smaller feature, for example a CMOS field-effect transistor ("FET") transistor having a gate length of 0.15-micron or less, there is a need for new technology to go beyond photolithography capabilities for miniaturization.